Computer Architecture: Complete Notes for Students and Competitive Exams
Computer Architecture explains how a computer system is designed and how the CPU, memory, input/output devices, and communication paths work together to execute programs.
These notes cover the foundations of computer architecture, including CPU organization, instruction sets, addressing modes, memory hierarchy, cache memory, pipelining, I/O, and parallel processing.
1. Introduction to Computer Architecture
Computer Architecture describes the functional design of a computer system. It explains how instructions are represented, how the processor executes them, how memory is accessed, and how hardware components communicate.
Whenever a program runs, the computer must fetch instructions, decode their meaning, execute the required operations, and store or display the result. Computer Architecture helps us understand what happens during this process.
Computer Architecture vs Computer Organization
Computer Architecture and Computer Organization are related, but they are not exactly the same. Architecture focuses on the features visible to programmers, while organization focuses on how those features are implemented in hardware.
| Computer Architecture | Computer Organization |
|---|---|
| Describes what the computer system does. | Describes how the system implements those functions. |
| Focuses on programmer-visible features. | Focuses on hardware implementation details. |
| Includes instruction sets, data types, and addressing modes. | Includes control signals, buses, hardware units, and interconnections. |
| Defines the functional behaviour of the system. | Explains how the hardware provides that behaviour. |
2. Basic Structure of a Computer
Most computer systems contain a processor, memory, input/output components, and communication paths between them. Each component has a specific role, but the system works only when these components cooperate.
Major Components
- Central Processing Unit (CPU): Executes instructions and performs calculations and logical operations.
- Memory Unit: Stores programs, instructions, and data currently needed by the computer.
- Input/Output Devices: Allow the computer to communicate with users and external devices.
- System Interconnection: Provides communication between the CPU, memory, and I/O components.
Basic Computer Structure
CPU ↔ System Interconnection (Bus) ↔ Main Memory and I/O Devices
The CPU, memory, and I/O devices communicate through system interconnections, commonly implemented using one or more buses.
Von Neumann Architecture
In the Von Neumann model, instructions and data are stored in the same main memory. They generally share communication paths when transferred between memory and the processor.
The processor repeatedly fetches an instruction, decodes it, executes it, and then moves to the next instruction. This process is called the fetch-decode-execute cycle.
Harvard Architecture
Harvard Architecture keeps instruction memory and data memory separate. It can use separate paths for instruction access and data access, allowing both activities to occur simultaneously in suitable designs.
| Von Neumann Architecture | Harvard Architecture |
|---|---|
| Instructions and data share the same memory. | Instructions and data use separate memories. |
| A common path may be used for instruction and data transfers. | Separate paths can support simultaneous instruction and data access. |
| Simple and flexible memory arrangement. | Can provide higher memory-access parallelism. |
3. CPU Organization
The Central Processing Unit, or CPU, is responsible for executing program instructions. It receives instructions, processes data, and produces results.
Main Components of the CPU
- Control Unit (CU): Coordinates processor activities and generates the control signals needed to execute instructions.
- Arithmetic Logic Unit (ALU): Performs arithmetic operations such as addition and subtraction, as well as logical operations such as AND, OR, and comparison.
- Registers: Small, very fast storage locations inside the CPU that hold data, instructions, addresses, and intermediate results.
- CPU Interconnections: Internal paths that allow CPU components to communicate.
Important CPU Registers
- Program Counter (PC): Contains the address of the next instruction to be fetched.
- Instruction Register (IR): Holds the instruction currently being decoded or executed.
- Memory Address Register (MAR): Holds the address of the memory location involved in a read or write operation.
- Memory Data Register (MDR): Holds data being transferred to or from memory. It is also called the Memory Buffer Register in some textbooks.
- Accumulator: A register traditionally used to store arithmetic results or intermediate values in certain processor designs.
4. Instruction Cycle
The processor repeatedly follows a sequence of steps to execute instructions. The exact stages vary by processor and instruction type, but the simplified instruction cycle includes the following:
- Fetch: The CPU uses the Program Counter to locate and read the next instruction from memory.
- Decode: The control unit interprets the instruction and identifies the required operation and operands.
- Execute: The processor performs the required arithmetic, logical, branch, or memory operation.
- Write Back, when required: The result is written to a register or memory location.
After the instruction has been processed, the CPU continues with the next instruction. Branch and jump instructions can change the normal sequence by changing the Program Counter.
5. Instruction Set Architecture and Addressing Modes
Instruction Set Architecture
An Instruction Set Architecture (ISA) defines the instructions, registers, data types, addressing modes, and programmer-visible behaviour supported by a processor. It forms an important boundary between software and hardware.
Instruction Format
An instruction generally contains an operation code and information about the operands. The exact instruction format depends on the processor architecture.
- Opcode: Specifies the operation the processor should perform.
- Operands: Specify the data, registers, or memory locations involved in the operation.
CISC and RISC
CISC and RISC are two broad approaches to instruction-set design. Modern processors may combine ideas from both approaches, but the following comparison is useful for basic understanding.
| CISC | RISC |
|---|---|
| Traditionally provides a larger and feature-rich instruction set. | Traditionally uses a smaller set of simpler instructions. |
| Instructions may perform relatively complex operations. | Instructions generally perform simpler operations. |
| May support many addressing modes. | Usually uses fewer and simpler addressing modes. |
| Instruction formats can be more complex. | Instruction formats are often designed for simpler decoding. |
| Example: x86 family. | Examples: ARM and MIPS. |
Addressing Modes
Addressing modes describe how an instruction identifies the operand it needs. Different addressing modes provide different ways to locate data in instructions, registers, or memory.
- Immediate Addressing: The operand value is included directly in the instruction.
- Direct Addressing: The address field identifies the memory location containing the operand.
- Indirect Addressing: The address field identifies a location that contains the actual operand address.
- Register Addressing: The operand is stored in a processor register.
- Register Indirect Addressing: A register contains the memory address of the operand.
- Indexed Addressing: The effective address is calculated using a base address and an index value.
- Relative Addressing: The effective address is calculated relative to the Program Counter or another reference point.
6. Instruction Pipelining
Instruction pipelining improves processor throughput by overlapping the stages of multiple instructions. Instead of waiting for one instruction to finish completely, different instructions can occupy different pipeline stages at the same time.
Common Five-Stage Pipeline
- Instruction Fetch (IF): The processor fetches the instruction from memory.
- Instruction Decode (ID): The instruction is decoded and required registers are identified or read.
- Execute (EX): The required arithmetic, logical, or address-calculation operation is performed.
- Memory Access (MEM): Memory is accessed when the instruction performs a load or store operation.
- Write Back (WB): The result is written back to the required register.
Pipeline Hazards
A pipeline cannot always operate at its ideal speed. Situations that interrupt the normal flow of instructions are called pipeline hazards.
- Structural Hazard: Two pipeline stages require the same hardware resource at the same time.
- Data Hazard: An instruction depends on data produced by an earlier instruction that has not completed the required stage.
- Control Hazard: A branch or jump changes the program flow after the processor has already fetched later instructions.
7. Memory Hierarchy and Cache Memory
A computer uses several kinds of storage because no single memory technology can provide maximum speed, maximum capacity, and minimum cost at the same time.
Memory Hierarchy
- Registers: Very small and extremely fast storage inside the CPU.
- Cache Memory: Fast memory that stores frequently or recently used data and instructions close to the processor.
- Main Memory (RAM): Stores programs and data actively being used by the computer.
- Secondary Storage: Provides large, persistent storage through devices such as SSDs and HDDs.
Memory Hierarchy
Registers → Cache → Main Memory (RAM) → Secondary Storage
Moving downward generally means greater capacity and lower cost per bit, but longer access time.
Locality of Reference
Programs often access data in predictable patterns. This behaviour is called locality of reference and is one reason cache memory works effectively.
- Temporal Locality: If a program accesses data or an instruction, it is likely to access the same item again soon.
- Spatial Locality: If a program accesses one memory location, it is likely to access nearby locations soon.
Cache Mapping Techniques
- Direct Mapping: Each main-memory block can be placed in one specific cache line.
- Fully Associative Mapping: A memory block can be placed in any cache line.
- Set-Associative Mapping: The cache is divided into sets, and a block can be placed in one of the lines in its assigned set.
Cache Performance Terms
- Cache Hit: The requested data is found in the cache.
- Cache Miss: The requested data is not found in the cache and must be fetched from another memory level.
- Hit Rate: The percentage of memory accesses successfully served by the cache.
- Miss Rate: The percentage of memory accesses not found in the cache.
- Hit Time: The time needed to access data found in the cache.
- Miss Penalty: The additional time needed to obtain data after a cache miss.
8. Input/Output Organization
Input/Output Organization explains how the processor communicates with external devices, such as keyboards, displays, storage devices, printers, and network interfaces.
I/O Transfer Methods
- Programmed I/O: The CPU controls the I/O operation and repeatedly checks device status.
- Interrupt-Driven I/O: The device interrupts the CPU when it needs attention or when an operation is complete.
- Direct Memory Access (DMA): A DMA controller transfers blocks of data between an I/O device and main memory with limited CPU involvement.
I/O Registers
- Data Register: Holds data being transferred between the device, CPU, or memory.
- Status Register: Stores information about the current state of the device.
- Control Register: Stores commands or control information used to operate the device.
9. Parallel Processing and Multiprocessor Systems
Parallel processing means performing multiple computations at the same time. A system can use multiple processing elements to work on different parts of a task concurrently.
Flynn's Taxonomy
Flynn's Taxonomy classifies computer architectures according to the number of instruction streams and data streams they process.
- SISD (Single Instruction, Single Data): A single instruction stream operates on a single data stream.
- SIMD (Single Instruction, Multiple Data): The same instruction operates on multiple data elements.
- MISD (Multiple Instruction, Single Data): Multiple instruction streams operate on a single data stream. This is uncommon in general-purpose computing.
- MIMD (Multiple Instruction, Multiple Data): Multiple processors execute different instructions on different data.
Examples of Parallel Systems
- Vector Processors: Perform operations on vectors or groups of data.
- Array Processors: Use multiple processing elements to operate on data in parallel.
- Multiprocessor Systems: Use multiple processors or CPU cores to execute tasks concurrently.
- Distributed Systems: Use multiple networked computers with separate memory resources to work on a larger task.
Shared Memory and Distributed Memory
| Shared Memory System | Distributed Memory System |
|---|---|
| Processors access a common memory space. | Each processing unit has its own local memory. |
| Processors can communicate through shared memory. | Processors commonly communicate through message passing. |
| Programming can be simpler for some applications. | Can provide strong scalability for suitable workloads. |
| UMA and NUMA are shared-memory organizations. | Common in clusters and distributed-computing environments. |
UMA and NUMA
In a Uniform Memory Access (UMA) system, processors generally have similar access time to shared memory. In a Non-Uniform Memory Access (NUMA) system, memory-access time can vary depending on the processor and memory location involved.
Interconnection Networks
- Bus: A simple communication structure, but bandwidth and scalability can become limitations.
- Crossbar Switch: Provides multiple possible processor-to-memory connections, but needs more hardware.
- Multistage Interconnection Network: Uses several switching stages to balance connectivity, cost, and scalability.
10. Common Mistakes Students Make
- Architecture vs Organization: Architecture describes programmer-visible behaviour; organization describes implementation details.
- Cache vs RAM: Cache is smaller and faster than RAM and is used to reduce average memory-access time.
- PC vs IR: The Program Counter identifies the next instruction to fetch, while the Instruction Register holds the current instruction.
- Data Hazard vs Control Hazard: A data hazard involves instruction dependencies, while a control hazard involves changes in program flow.
- DMA: DMA reduces CPU involvement in individual transfers; it does not remove CPU involvement completely.
- Pipelining: Pipelining improves throughput, but hazards and stalls can reduce its performance benefit.
11. Quick Revision
- Computer Architecture describes the functional design of a computer system.
- Computer Organization describes how the architecture is implemented in hardware.
- The CPU includes the Control Unit, ALU, registers, and internal interconnections.
- The PC stores the address of the next instruction, while the IR stores the current instruction.
- Von Neumann Architecture stores data and instructions together; Harvard Architecture separates them.
- RISC uses simpler instructions, while CISC traditionally uses more complex instructions.
- Pipelining overlaps instruction stages to improve throughput.
- Cache memory stores frequently used data and instructions close to the CPU.
- DMA transfers data between I/O devices and memory with limited CPU involvement.
- SIMD applies the same instruction to multiple data elements, while MIMD executes different instructions on different data.
- UMA has similar shared-memory access time; NUMA can have different access times.
12. Practice Questions
- What is the difference between Computer Architecture and Computer Organization?
- How does Von Neumann Architecture differ from Harvard Architecture?
- What are the main components of the CPU?
- What is the purpose of the Program Counter?
- What is an Instruction Set Architecture?
- Explain immediate, direct, and register-indirect addressing modes.
- What are structural, data, and control hazards in a pipeline?
- Why is cache memory used between the CPU and main memory?
- What is the difference between temporal locality and spatial locality?
- How does DMA reduce CPU involvement in I/O operations?
- Explain SISD, SIMD, MISD, and MIMD.
- What is the difference between UMA and NUMA?
Conclusion
Computer Architecture is a fundamental Computer Science subject because it connects software instructions with the hardware that executes them. Concepts such as CPU organization, instruction sets, addressing modes, memory hierarchy, cache, pipelining, I/O, and parallel processing help explain how modern computer systems work.
For exam preparation, learn the basic definitions first, compare related concepts, draw simple diagrams, and practise numerical and descriptive questions. Understanding the relationships between CPU, memory, cache, and I/O is more valuable than memorising isolated definitions.